1. Field of Invention
The present invention relates to a method for manufacturing devices that have a thick gate oxide. More particularly, the present invention relates to a method for forming gate oxide having different thickness over the input/output device area and core device area through thermal oxidation processes.
2. Description of Related Art
Advances in integrated circuit fabricating techniques have reduced the dimensions of semiconductor devices continuously. Consequently, the gate dielectric and gate oxide layers of a field effect transistor are becoming thinner and thinner. Although a thin gate oxide layer allows device dimensions to be reduced, a lower operational voltage source is needed. Since the external voltage is not low enough to directly supply the miniaturized internal devices, a certain number of devices having a thicker gate oxide layer must be used as a medium for linking with external voltage source. Through these specially thickened gate oxide devices, a high voltage can be gradually transformed into a lower operational voltage suitable for use in ordinary devices, which have a thin gate oxide layer. Therefore, a method for fabricating integrated circuit devices having a thick gate oxide is invented.
In the manufacture of gate oxide layer, usually the double thickness gate oxide layer is used for covering the input/output (I/O) devices, while the thinner gate oxide layer is formed over the core devices. In a conventional method, a first gate oxide layer is usually formed over a substrate in the beginning. FIGS. 1A through 1C are cross-sectional views showing the progression of manufacturing steps in forming a thin and a thick gate oxide layer over a substrate in a conventional method. First, as shown in FIG. 1A, shallow trench isolation 11 is formed over the silicon substrate 10 for separating the input/output device area 12 and core device area 13. Then, an oxidation reaction is conducted to form a first gate oxide layer 14 over the device areas above the silicon substrate 10. Subsequently, a photoresist layer 15 is formed over the device areas. Then, the photoresist layer 15 is patterned to remove the photoresist layer above the core device area 13 using photolithographic and etching processes, and obtained a structure as shown in FIG. 1A.
Next, as shown in FIG. 1B, the first gate oxide layer that is not covered by the photoresist layer 15 is completely etched away. Subsequently, the photoresist layer 15 is also removed forming a cross-sectional structure as shown in FIG. 1B. Thereafter, as shown in FIG. 1C, another oxidation reaction is carried out to form a second gate oxide layer 16. The second gate oxide layer 16 may or may not be of the same thickness as the first gate oxide layer 14. Hence, two gate oxide layers, namely, the first gate oxide layer 14 and the second gate oxide layer 16, are formed above the input/output device area 12. On the other hand, only one gate oxide layer, namely, the second gate oxide layer 16, are formed above the core device area 13. Consequently, different device areas will have different gate oxide layer thickness, and therefore able to provide the characteristics each type of devices demand.
However, before depositing any gate oxide layers, a number of prior steps required for creating the necessary device characteristics in different device areas are usually performed. For example, threshold voltage can be adjusted through controlling the level and concentration of ions doped into the substrate. However, the heat generated by the first thermal oxidation can easily make ions out-diffuse into the first gate oxide layer, this is especially serious when one of the doped ions is boron. Consequently, since a portion of the first gate oxide layer is etched away, some of the out-diffused ions will be carried away along with the gate oxide material. This will result in a change in the distribution of level and concentration for the doped ions, thereby leading to a change in the threshold voltage characteristic. Because it is very difficult to estimate the effect of gate oxide etching on the amount of doped ions removed, uniform device properties are difficult to get.
In light of the foregoing, there is a need in the art to provide a better method for forming a double thickness gate oxide layer.